In high-speed data transmission used in a Universal Serial Bus (USB), a Serial Advanced Technology Attachment (SATA), and so on between sending and receiving circuits, a clock used for a logical determination (determination of 0 or 1) of the receiving data is restored from the receiving data. In order to correctly perform the logical determination of the receiving data, the phase of the clock restored by the receiving circuit is adjusted by a feedback circuit included inside the receiving circuit so that a phase difference between the phase of the clock and the phase of the receiving data is constant. As such, the clock for the logical determination of the receiving data is reproduced by the receiving circuit, and the sending data is reproduced by performing the logical determination of the receiving data using the reproduced clock. These reproductions are called Clock and Data Recovery (CDR).
Japanese Laid-open Patent Publication No. 11-203785 and Japanese Laid-open Patent Publication No. 61-269421 disclose techniques concerning a phase adjustment.